Table of Contents
Advertisement
Section 4 Exception Handling
4.6
Interrupts
4.6.1
Interrupt Sources
Interrupt sources are NMI, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 4.7.
Table 4.7
Interrupt Sources
Type
Source
NMI
NMI pin (external input)
Pins IRQ0 to IRQ11 (external input)
IRQ0 to IRQ11
On-chip
Watchdog timer (WDT)
peripheral
A/D converter
module
16-bit timer pulse unit (TPU)
8-bit timer (TMR)
Serial communications interface (SCI)
Different vector numbers and vector table offsets are assigned to different interrupt sources. For
vector number and vector table offset, see table 5.2, Interrupt Sources, Vector Address Offsets,
and Interrupt Priority in section 5, Interrupt Controller.
4.6.2
Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiple-interrupt control. The source to start interrupt exception handling and the vector address
differ depending on the product. For details, see section 5, Interrupt Controller.
The interrupt exception handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the interrupt source is generated,
the start address of the exception service routine is loaded from the vector table to PC, and
program execution starts from that address.
Rev.2.00 Jun. 28, 2007 Page 78 of 666
REJ09B0311-0200
Number of Sources
1
12
1
1
26
12
16
Advertisement
Table of Contents
