Renesas H8SX/1650 Hardware Manual page 183

Table 6.10 Area 3 External Interface
Interface
Basic bus interface
Byte control SRAM interface
Address/data multiplexed I/O
interface
Setting prohibited
(5)
Area 4
In externally extended mode, all of area 4 is external address space.
When area 4 external address space is accessed, the CS4 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O
interface can be selected for area 4 by bit MPXE4 in MPXCR and bit BCSEL4 in SRAMCR.
Table 6.11 shows the external interface of area 4.
Table 6.11 Area 4 External Interface
Interface
Basic bus interface
Byte control SRAM interface
Address/data multiplexed I/O
interface
Setting prohibited
(6)
Area 5
Area 5 includes the on-chip RAM and access prohibited spaces. In external extended
mode, area 5, other than the on-chip RAM and access-prohibited spaces, is external address space.
Note that the on-chip RAM is enabled when the RAME bit in SYSCR are set to 1. If the RAME
bit in SYSCR is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are an
external address space. For details, see section 3, MCU Operating Modes.
MPXE3 of MPXCR
0
0
1
1
MPXE4 of MPXCR
0
0
1
1
Section 6 Bus Controller (BSC)
Register Setting
BCSEL3 of SRAMCR
0
1
0
1
Register Setting
BCSEL4 of SRAMCR
0
1
0
1
Rev.2.00 Jun. 28, 2007 Page 161 of 666
REJ09B0311-0200