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18.3
Multi-Clock Function
When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, the clock
frequency changes at the end of the bus cycle. The CPU and bus masters operate on the operating
clock specified by bits ICK2 to ICK0. The peripheral modules operate on the operating clock
specified by bits PCK2 to PCK0. The external bus clock operates on the operating clock specified
by bits BCK2 to BCK0.
Even if the frequencies specified by bits PCK2 to PCK0 and BCK2 to BCK0 are higher than the
frequency specified by bits ICK2 to ICK0, the specified values are not reflected in the peripheral
module and external bus clocks. The peripheral module and external bus clocks are restricted to
the operating clock specified by bits ICK2 to ICK0.
18.4
Module Stop Function
Module stop function can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCRA, MSTPCRB, or MSTPCRC is set to 1, module
operation stops at the end of the bus cycle and a transition is made to the module stop state. The
CPU continues operating independently.
When the corresponding MSTP bit is cleared to 0, the module stop state is cleared and the module
starts operating at the end of the bus cycle. In the module stop state, the internal states of modules
other than the SCI are retained.
After the reset state is cleared, all modules other than the DTC and on-chip RAM are in the
module stop state.
The registers of the module for which the module stop state is selected cannot be read from or
written to.
Section 18 Power-Down States
Rev.2.00 Jun. 28, 2007 Page 573 of 666
REJ09B0311-0200
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