Renesas H8SX/1650 Hardware Manual page 15

8.1.1 Data Direction Register (PnDDR) (n = 1 to 3, 6, A, B, D to F, H, and I) ......... 258
8.1.2 Data Register (PnDR) (n = 1 to 3, 6, A, B, D to F, H, and I)............................ 259
8.1.3 Port Register (PORTn) (n = 1 to 3, 5, 6, A, B, D to F, H, and I) ...................... 259
8.1.4 Input Buffer Control Register (PnICR)
(n = 1 to 3, 5, 6, A, B, D to F, H, and I)............................................................ 260
8.1.5 Pull-Up MOS Control Register (PnPCR) (n = D to F, H, and I)....................... 261
8.1.6 Open-Drain Control Register (PnODR) (n = 2 and F) ...................................... 262
8.2 Output Buffer Control....................................................................................................... 262
8.2.1 Port 1................................................................................................................. 262
8.2.2 Port 2................................................................................................................. 265
8.2.3 Port 3................................................................................................................. 269
8.2.4 Port 5................................................................................................................. 273
8.2.5 Port 6................................................................................................................. 274
8.2.6 Port A................................................................................................................ 276
8.2.7 Port B ................................................................................................................ 280
8.2.8 Port D................................................................................................................ 282
8.2.9 Port E ................................................................................................................ 282
8.2.10 Port F ................................................................................................................ 283
8.2.11 Port H................................................................................................................ 286
8.2.12 Port I ................................................................................................................. 286
8.3 Port Function Controller ................................................................................................... 292
8.3.1 Port Function Control Register 0 (PFCR0)....................................................... 292
8.3.2 Port Function Control Register 1 (PFCR1)....................................................... 293
8.3.3 Port Function Control Register 2 (PFCR2)....................................................... 294
8.3.4 Port Function Control Register 4 (PFCR4)....................................................... 296
8.3.5 Port Function Control Register 6 (PFCR6)....................................................... 297
8.3.6 Port Function Control Register 9 (PFCR9)....................................................... 298
8.3.7 Port Function Control Register B (PFCRB)...................................................... 300
8.3.8 Port Function Control Register C (PFCRC)...................................................... 301
8.4 Usage Notes ...................................................................................................................... 303
8.4.1 Notes on Input Buffer Control Register (ICR) Setting ..................................... 303
8.4.2 Notes on Port Function Control Register (PFCR) Settings............................... 303
Section 9 16-Bit Timer Pulse Unit (TPU) .........................................................305
9.1 Features............................................................................................................................. 305
9.2 Input/Output Pins.............................................................................................................. 309
9.3 Register Descriptions........................................................................................................ 310
9.3.1 Timer Control Register (TCR).......................................................................... 312
9.3.2 Timer Mode Register (TMDR) ......................................................................... 318
9.3.3 Timer I/O Control Register (TIOR) .................................................................. 319
Rev.2.00 Jun. 28, 2007 Page xv of xxii