Section 5 Interrupt Controller; Features - Renesas H8SX/1650 Hardware Manual

5.1

Features

• Two interrupt control modes
Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the
interrupt control register (INTCR).
• Priority can be assigned by the interrupt priority register (IPR)
IPR provides for setting interrupt priory. Eight levels can be set for each module for all
interrupts except for the interrupt requests listed below. The following seven interrupt requests
are given priority of 8, therefore they are accepted at all times.
 NMI
 Illegal instructions
 Trace
 Trap instructions
 CPU address error
 DMA address error (occurred in the DTC)
 Sleep instruction
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
• Thirteen external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level
sensing, can be selected for IRQ11 to IRQ0.
• DTC control
DTC can be activated by means of interrupts.
• CPU priority control function
The priority levels can be assigned to the CPU and DTC. The priority level of the CPU can be
automatically assigned on an exception generation. Priority can be given to the CPU interrupt
exception handling over that of the DTC transfer.

Section 5 Interrupt Controller

Section 5 Interrupt Controller
Rev.2.00 Jun. 28, 2007 Page 85 of 666
REJ09B0311-0200