Next Data Registers H, L (Ndrh, Ndrl) - Renesas H8SX/1650 Hardware Manual

• PODRL
Bit Bit Name
7 POD7
6 POD6
5 POD5
4 POD4
3 POD3
2 POD2
1 POD1
0 POD0
10.3.3

Next Data Registers H, L (NDRH, NDRL)

NDRH and NDRL store the next data for pulse output. The NDR addresses differ depending on
whether pulse output groups have the same output trigger or different output triggers.
• NDRH
7
Bit
NDR15
Bit Name
0
Initial Value
R/W
R/W
• NDRL
7
Bit
NDR7
Bit Name
0
Initial Value
R/W
R/W
Initial
Value R/W Description
0 R/W Output Data Register 7 to 0
0 R/W For bits which have been set to pulse output by NDERL,
the output trigger transfers NDRL values to this register
0 R/W
during PPG operation. While NDERL is set to 1, the CPU
0 R/W
cannot write to this register. While NDERL is cleared, the
initial output value of the pulse can be set.
0 R/W
0 R/W
0 R/W
0 R/W
6 5
NDR14 NDR13
0 0
R/W R/W
6 5
NDR6 NDR5
0 0
R/W R/W
Section 10 Programmable Pulse Generator (PPG)
4 3
NDR12 NDR11
0 0
R/W R/W
4 3
NDR4 NDR3
0 0
R/W R/W
Rev.2.00 Jun. 28, 2007 Page 395 of 666
2 1
NDR10 NDR9
0 0
R/W R/W
2 1
NDR2 NDR1
0 0
R/W R/W
REJ09B0311-0200
0
NDR8
0
R/W
0
NDR0
0
R/W