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Bφ
A23 to A0
CS7 to CS0
AS
BS
RD/WR
Read
RD
(RDNn = 1)
D15 to D0
RD/WR
RD
Read
(RDNn = 0)
D15 to D0
RD/WR
Write
LHWR, LLWR
D15 to D0
Figure 20.11 Basic Bus Timing: 2-State Access (CS Assertion Period Extended)
T
T
h
t
AD
t
CSD1
t
AS1
t
ASD
t
BSD
t
BSD
t
RWD
t
AS3
t
RWD
t
AS3
t
RWD
t
AS3
t
t
WDD
WDS2
Section 20 Electrical Characteristics
T
1
2
t
ASD
t
t
RSD1
RSD1
t
t
t
RDS1
RDH1
AC5
t
t
RSD1
RSD2
t
t
t
RDS2
RDH2
AC2
t
t
t
WRD2
WRD2
t
t
WSW1
WDH3
Rev.2.00 Jun. 28, 2007 Page 631 of 666
T
t
t
AH1
t
RWD
t
AH3
t
RWD
t
AH2
t
RWD
AH3
REJ09B0311-0200
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