Renesas H8SX/1650 Hardware Manual page 200

Section 6 Bus Controller (BSC)
Bφ
Address
CSn
AS
RD
Read
Data bus
LHWR, LLWR
Write
Data bus
BS
RD/WR
Note: n = 0 to 7
Figure 6.22 Example of Timing when Chip Select Assertion Period is Extended
Rev.2.00 Jun. 28, 2007 Page 178 of 666
REJ09B0311-0200
Bus cycle
T T
h 1
Write data
T T
2 3
Read data
T
t