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Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.4
CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Bit 7
Reserved
2
Channel
*
1, 2, 4, 5
0
0
0
0
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
Table 9.5
Input Clock Edge Selection
Clock Edge Selection
CKEG1
CKEG0
0
0
0
1
1
X
[Legend]
X:
Don't care
Rev.2.00 Jun. 28, 2007 Page 314 of 666
REJ09B0311-0200
Bit 6
Bit 5
CCLR1
CCLR0
0
0
0
1
1
0
1
1
Internal Clock
Counted at falling edge
Counted at rising edge
Counted at both edges
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
Input Clock
External Clock
Counted at rising edge
Counted at falling edge
Counted at both edges
1
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