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Section 6 Bus Controller (BSC)
(3)
External Bus Release Function and Software Standby
In this LSI, internal bus master operation does not stop even while the bus is released, as long as
the program is running in on-chip RAM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
Also, since clock oscillation halts in software standby mode, if the BREQ signal goes low in this
mode, indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby mode.
Note that BACK and BREQO goes Hi-Z during software standby.
BREQO Output Timing
(4)
When the BREQOE bit is set to 1 and the BREQO signal is output, both the BREQO and BACK
signals may go low simultaneously.
This will occur if the next external access request occurs while internal bus arbitration is in
progress after the chip samples a low level of the BREQ signal.
Rev.2.00 Jun. 28, 2007 Page 216 of 666
REJ09B0311-0200
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