Exception Handling By Illegal Instruction - Renesas H8SX/1650 Hardware Manual

Renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series
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4.7.3

Exception Handling by Illegal Instruction

The illegal instructions are general illegal instructions and slot illegal instructions. The exception
handling by the general illegal instruction starts when an undefined code is executed. The
exception handling by the slot illegal instruction starts when a particular instruction (e.g. its code
length is two words or more, or it changes the PC contents) at a delay slot (immediately after a
delayed branch instruction) is executed. The exception handling by the general illegal instruction
and slot illegal instruction is always executable in the program execution state.
The exception handling is as follows:
1. The contents of PC, CCR, and EXR are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. An exception handling vector table address corresponding to the occurred exception is
generated, the start address of the exception service routine is loaded from the vector table to
PC, and program execution starts from that address.
Table 4.10 shows the state of CCR and EXR after execution of illegal instruction exception
handling.
Table 4.10 Status of CCR and EXR after Illegal Instruction Exception Handling
Interrupt Control Mode
0
2
[Legend]
1:
Set to 1
0:
Cleared to 0
:
Retains the previous value.
CCR
I
UI
1
1
Section 4 Exception Handling
EXR
T
I2 to I0
0
Rev.2.00 Jun. 28, 2007 Page 81 of 666
REJ09B0311-0200

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