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Section 11 8-Bit Timers (TMR)
11.3.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in
TCR and bits ICKS1 and ICKS0 in TCCR are used to select a clock. TCNT can be cleared by an
external reset input signal, compare match A signal, or compare match B signal. Which signal is to
be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When TCNT overflows from
H'FF to H'00, bit OVF in TCSR is set to 1. TCNT is initialized to H'00.
Bit
7
6
Bit Name
Initial Value
0
0
R/W
R/W
R/W
11.3.2
Time Constant Register A (TCORA)
TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction. The value in TCORA is
continually compared with the value in TCNT. When a match is detected, the corresponding
CMFA flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a
TCORA write cycle. The timer output from the TMO pin can be freely controlled by this compare
match signal (compare match A) and the settings of bits OS1 and OS0 in TCSR. TCORA is
initialized to H'FF.
Bit
7
6
Bit Name
Initial Value
1
1
R/W
R/W
R/W
Rev.2.00 Jun. 28, 2007 Page 416 of 666
REJ09B0311-0200
TCNT_0
5
4
3
2
0
0
0
0
R/W
R/W
R/W
R/W
TCORA_0
5
4
3
2
1
1
1
1
R/W
R/W
R/W
R/W
1
0
7
6
0
0
0
0
R/W
R/W
R/W
R/W
1
0
7
6
1
1
1
1
R/W
R/W
R/W
R/W
TCNT_1
5
4
3
2
0
0
0
0
R/W
R/W
R/W
R/W
TCORA_1
5
4
3
2
1
1
1
1
R/W
R/W
R/W
R/W
1
0
0
0
R/W
R/W
1
0
1
1
R/W
R/W
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