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Numerics
0-output/1-output .................................... 349
16-bit access space.................................. 165
16-bit counter mode................................ 430
16-bit timer pulse unit (TPU) ................. 305
8-bit access space.................................... 164
8-bit timers (TMR) ................................. 411
A
A/D conversion accuracy........................ 538
A/D converter ......................................... 525
Absolute accuracy................................... 538
Address error ............................................ 76
Address map ............................................. 68
Address/data multiplexed
I/O interface.................................... 158, 189
Addressing modes..................................... 50
All-module-clock-stop mode .......... 564, 575
Area 0 ..................................................... 159
Area 1 ..................................................... 159
Area 2 ..................................................... 160
Area 3 ..................................................... 160
Area 4 ..................................................... 161
Area 5 ..................................................... 161
Area 6 ..................................................... 162
Area 7 ..................................................... 163
Area division........................................... 153
Asynchronous mode ............................... 481
AT-cut parallel-resonance type............... 557
Available output signal
and settings in each port ......................... 287
Average transfer rate generator............... 450
B
Bφ clock output control .......................... 585
Index
Basic bus interface .......................... 157, 167
Big endian ............................................... 156
Bit rate..................................................... 471
Block diagram............................................. 8
Block transfer mode ................................ 239
Burst ROM interface....................... 157, 185
Bus arbitration......................................... 213
Bus configuration.................................... 145
Bus controller (BSC)............................... 121
Bus cycle division ................................... 233
Bus width ................................................ 156
Bus-released state...................................... 59
Byte control SRAM interface ......... 157, 179
C
Cascaded connection............................... 430
Cascaded operation ................................. 357
Chain transfer.......................................... 240
Chip select signals................................... 154
Clock pulse generator ............................. 553
Clock synchronization cycle (Tsy).......... 147
Clocked synchronous mode .................... 498
Compare match A ................................... 428
Compare match B ................................... 428
Compare match count mode ................... 430
Compare match signal............................. 427
CPU priority control
function over DTC .................................. 115
Crystal resonator ..................................... 557
D
D/A converter ......................................... 545
Data direction register............................. 258
Data register............................................ 259
Data transfer controller (DTC)................ 217
Rev.2.00 Jun. 28, 2007 Page 661 of 666
REJ09B0311-0200
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