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Table 8.5
Available Output Signals and Settings in Each Port
Output
Specification
Port
Signal Name
P1
2
SCK2_OE
0
TxD2_OE
P2
7
TIOCB5_OE
PO7_OE
6
TIOCA5_OE
TMO1_OE
TxD1_OE
PO6_OE
5
TIOCA4_OE
PO5_OE
4
TIOCB4_OE
SCK1_OE
PO4_OE
3
TIOCD3_OE
PO3_OE
Output
Signal
Signal Selection
Name
Register Settings
SCK2
TxD2
TIOCB5
PO7
TIOCA5
TMO1
TxD1
PO6
TIOCA4
PO5
TIOCB4
SCK1
PO4
TIOCD3
PO3
Peripheral Module Settings
When SCMR.SMIF = 1:
SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0,
SCR.CKE [1, 0] = 01 or while SMR.GM = 1
When SCMR.SMIF = 0:
SCR.TE = 1 or SCR.RE = 1
while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or
while SMR.C/A = 1, SCR.CKE 1 = 0
SCR.TE = 1
TPU.TIOR5.IOB3 = 0, TPU.TIOR5.IOB[1,0] = 01/10/11
NDERL.NDER7 = 1
TPU.TIOR5.IOA3 = 0, TPU.TIOR5.IOA[1,0] = 01/10/11
TCSR.OS3,2 = 01/10/11 or TCSR.OS[1,0] = 01/10/11
SCR.TE = 1
NDERL.NDER6 = 1
TPU.TIOR4.IOA3 = 0, TPU.TIOR4.IOA[1,0] = 01/10/11
NDERL.NDER5 = 1
TPU.TIOR4.IOB3 = 0, TPU.TIOR4.IOB[1,0] = 01/10/11
When SCMR.SMIF = 1:
SCR.TE = 1 or SCR.RE = 1 while
SMR.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1
When SCMR.SMIF = 0:
SCR.TE = 1 or SCR.RE = 1
while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or
while SMR.C/A = 1, SCR.CKE 1 = 0
NDERL.NDER4 = 1
TPU.TMDR.BFB = 0, TPU.TIORL3.IOD3 = 0,
TPU.TIORL3.IOD[1,0] = 01/10/11
NDERL.NDER3 = 1
Rev.2.00 Jun. 28, 2007 Page 287 of 666
Section 8 I/O Ports
REJ09B0311-0200
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