Renesas H8SX/1650 Hardware Manual page 491

Bit Bit Name
2 TEND
1 MPB
0 MPBT
Note: Only 0 can be written, to clear the flag.
*
Initial
Value R/W Description
1 R Transmit End
This bit is set to 1 when no error signal is sent from the
receiving side and the next transmit data is ready to be
transferred to TDR.
[Setting conditions]
•
•
[Clearing conditions]
•
•
0 R Multiprocessor Bit
Not used in smart card interface mode.
0 R/W Multiprocessor Bit Transfer
Write 0 to this bit in smart card interface mode.
Section 13 Serial Communication Interface (SCI)
When both the TE and ERS bits in SCR are 0
When ERS = 0 and TDRE = 1 after a specified time
passed after completion of 1-byte data transfer. The
set timing depends on the register setting as
follows:
When GM = 0 and BLK = 0, 2.5 etu after
transmission start
When GM = 0 and BLK = 1, 1.5 etu after
transmission start
When GM = 1 and BLK = 0, 1.0 etu after
transmission start
When GM = 1 and BLK = 1, 1.0 etu after
transmission start
When 0 is written to TEND after reading TEND = 1
When a TXI interrupt request is issued allowing
DTC to write the next data to TDR
Rev.2.00 Jun. 28, 2007 Page 469 of 666
REJ09B0311-0200