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Section 12 Watchdog Timer (WDT)
The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At
the same time, the WDT can also generate an internal reset signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
Figure 12.1 shows a block diagram of the WDT.
12.1
Features
• Selectable from eight counter input clocks
• Switchable between watchdog timer mode and interval timer mode
In watchdog timer mode
If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or
not the entire LSI is reset at the same time.
In interval timer mode
If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
(interrupt request
Internal reset signal*
[Legend]
TCSR:
TCNT:
RSTCSR:
Note: * An internal reset signal can be generated by the RSTCSR setting.
Interrupt
WOVI
control
signal)
WDTOVF
Reset
control
RSTCSR
Timer control/status register
Timer counter
Reset control/status register
Figure 12.1 Block Diagram of WDT
Overflow
Clock
Clock
select
TCNT
TCSR
Module bus
WDT
Rev.2.00 Jun. 28, 2007 Page 437 of 666
Section 12 Watchdog Timer (WDT)
Pφ/2
Pφ/64
Pφ/128
Pφ/512
Pφ/2048
Pφ/8192
Pφ/32768
Pφ/131072
Internal clocks
Bus
interface
REJ09B0311-0200
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