Renesas H8SX/1650 Hardware Manual page 335

Table 9.3 CCLR2 to CCLR0 (Channels 0 and 3)
Bit 7
Channel CCLR2
0, 3 0
0
0
0
1
1
1
1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Bit 6 Bit 5
CCLR1 CCLR0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Section 9 16-Bit Timer Pulse Unit (TPU)
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
2
capture*
TCNT cleared by TGRD compare match/input
2
capture*
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
Rev.2.00 Jun. 28, 2007 Page 313 of 666
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