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7.5.9
Number of DTC Execution Cycles
Table 7.9 shows the execution status for a single DTC data transfer, and table 7.10 shows the
number of cycles required for each execution.
Table 7.9
DTC Execution Status
Transfer
Vector
Information
Read
Read
Mode
I
J
1
Normal 1
0*
4*
1
Repeat 1
0*
4*
1
Block
1
0*
4*
transfer
[Legend]
P:
Block size (CRAH and CRAL value)
Notes: 1. When transfer information read is skipped
2. In full address mode operation
3. In short address mode operation
4. When the SAR or DAR is in fixed mode
5. When the SAR and DAR are in fixed mode
6. When a longword is transferred while an odd address is specified in the address
register
7. When a word is transferred while an odd address is specified in the address register or
when a longword is transferred while address 4n + 2 is specified
Transfer
Information
Write
L
2
3
1
2.3
3*
0*
3*
2*
2
3
1
2.3
3*
0*
3*
2*
2
3
1
2.3
3*
0*
3*
2*
Section 7 Data Transfer Controller (DTC)
Data Read
L
4
5
6
7
1*
3*
2*
1
4
5
6
7
1*
3*
2*
1
4
5
7
1*
3•P
2•P*
1•P 3•P
6
*
Rev.2.00 Jun. 28, 2007 Page 243 of 666
Internal
Data Write
Operation
M
N
6
7
3*
2*
1
1
0*
6
7
3*
2*
1
1
0*
7
1
0*
2•P*
1•P
6
*
REJ09B0311-0200
1
1
1
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