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Section 2 CPU
2.8
Addressing Modes and Effective Address Calculation
The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a
subset of these addressing modes.
Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to
specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.12 Addressing Modes
No. Addressing Mode
1
Register direct
2
Register indirect
3
Register indirect with displacement
4
Index register indirect with displacement
5
Register indirect with post-increment
Register indirect with pre-decrement
Register indirect with pre-increment
Register indirect with post-decrement
6
Absolute address
7
Immediate
8
Program-counter relative
9
Program-counter relative with index register
10
Memory indirect
11
Extended memory indirect
Rev.2.00 Jun. 28, 2007 Page 50 of 666
REJ09B0311-0200
Symbol
Rn
@ERn
@(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn)
@(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L)
@(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L)
@ERn+
@−ERn
@+ERn
@ERn−
@aa:8/@aa:16/@aa:24/@aa:32
#xx:3/#xx:4/#xx:8/#xx:16/#xx:32
@(d:8,PC)/@(d:16,PC)
@(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC)
@@aa:8
@@vec:7
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