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Section 6 Bus Controller (BSC)
When area 5 external address space is accessed, the CS5 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O
interface can be selected for area 5 by the MPXE5 bit in MPXCR and the BCSEL5 bit in
SRAMCR. Table 6.12 shows the external interface of area 5.
Table 6.12 Area 5 External Interface
Interface
Basic bus interface
Byte control SRAM interface
Address/data multiplexed I/O
interface
Setting prohibited
(7)
Area 6
Area 6 includes internal I/O registers. In external extended mode, area 6 other than on-chip I/O
register area is external address space.
When area 6 external address space is accessed, the CS6 signal can be output.
Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O
interface can be selected for area 6 by the MPXE6 bit in MPXCR and the BCSEL6 bit in
SRAMCR. Table 6.13 shows the external interface of area 6.
Table 6.13 Area 6 External Interface
Interface
Basic bus interface
Byte control SRAM interface
Address/data multiplexed I/O
interface
Setting prohibited
Rev.2.00 Jun. 28, 2007 Page 162 of 666
REJ09B0311-0200
MPXE5 of MPXCR
0
0
1
1
MPXE6 of MPXCR
0
0
1
1
Register Setting
BCSEL5 of SRAMCR
0
1
0
1
Register Setting
BCSEL6 of SRAMCR
0
1
0
1
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