Extension Of Chip Select (Cs) Assertion Period - Renesas H8SX/1650 Hardware Manual

Section 6 Bus Controller (BSC)
6.9.9

Extension of Chip Select (CS) Assertion Period

In the address/data multiplexed interface, the extension cycles can be inserted before and after the
bus cycle. For details, see section 6.6.6, Extension of Chip Select (CS) Assertion Period.
Figure 6.32 shows an example of the chip select (CS) assertion period extension timing.
Bφ
Address bus
CSn
AH
RD
Read
D15 to D0
LHWR
LLWR
Write
D15 to D0
BS
RD/WR
Note: n = 3 to 7
Figure 6.32 Chip Select (CS) Assertion Period Extension Timing in Data Cycle
When consecutively reading from the same area connected to a peripheral LSI whose data hold
time is long, data outputs from the peripheral LSI and this LSI may conflict. Inserting the chip
select assertion period extension cycle after the access cycle can avoid the data conflict.
Rev.2.00 Jun. 28, 2007 Page 196 of 666
REJ09B0311-0200
Address cycle
T
T
ma1 ma2
Address
Address
Bus cycle
Data cycle
T T T
h 1
Write data
T
2 t
Read data