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Data transfer instructions.......................... 39
Direct convention ................................... 507
Double-buffered structure....................... 481
DTC vector address ................................ 229
DTC vector address offset ...................... 229
E
Effective address ...................................... 56
Endian and data alignment ..................... 163
Endian format ......................................... 156
Error signal ............................................. 507
Exception handling ................................... 69
Exception handling vector table ............... 70
Exception-handling state .......................... 59
Extension of chip select (CS)
assertion period....................................... 177
External access bus................................. 145
External bus ............................................ 150
External bus clock (Bφ) .................. 146, 553
External bus interface ............................. 155
External clock......................................... 558
External interrupts .................................. 100
F
Free-running count operation ................. 347
Frequency divider ................................... 553
Full address mode................................... 228
Full-scale error........................................ 538
G
General registers ....................................... 25
H
Hardware standby mode ................. 564, 580
Rev.2.00 Jun. 28, 2007 Page 662 of 666
REJ09B0311-0200
I
I/O ports .................................................. 251
ID code.................................................... 492
Idle cycle................................................. 198
Illegal instruction ...................................... 81
Index register ............................................ 25
Initial register values................................. 29
Input buffer control register .................... 260
Internal interrupts.................................... 101
Internal peripheral bus ............................ 145
Internal system bus ................................. 145
Interrupt .................................................... 78
Interrupt control mode 0 ......................... 106
Interrupt control mode 2 ......................... 108
Interrupt controller.................................... 85
Interrupt exception handling sequence ... 110
Interrupt exception handling
vector table.............................................. 102
Interrupt response times.......................... 111
Interrupt sources ..................................... 100
Interrupt sources and vector
address offsets......................................... 102
Interval timer .......................................... 444
Interval timer mode................................. 444
Inverse convention.................................. 508
IRQn interrupts ....................................... 100
L
Little endian ............................................ 156
M
Mark state ....................................... 481, 519
MCU operating modes.............................. 61
Memory map............................................. 23
Mode 4 ...................................................... 66
Mode 5 ...................................................... 66
Mode pin................................................... 61
Module stop function .............................. 573
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