Renesas H8SX/1650 Hardware Manual page 64

Section 2 CPU
Instruction Size
DIVXU B/W
DIVU W/L
DIVXS B/W
DIVS W/L
CMP B/W/L
NEG B/W/L
EXTU W/L
EXTS W/L
TAS B

MAC

CLRMAC
Rev.2.00 Jun. 28, 2007 Page 42 of 666
REJ09B0311-0200
Function
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16 bits
÷ 16 bits → 16-bit quotient or 32 bits ÷ 32 bits → 32-bit quotient.
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
16 bits → 16-bit quotient or 32 bits ÷ 32 bits → 32-bit quotient.
(EAd) − #IMM, (EAd) − (EAs)
Compares data between immediate data, general registers, and memory
and stores CCR bits according to the result.
0 − (EAd) → (EAd)
Takes the two's complement (arithmetic complement) of the contents of a
general register or a memory location.
(EAd) (zero extension) → (EAd)
Extends the lower 8 or 16 bits of data in a general register or a memory
location to word or longword size by padding with 0s.
The lower eight bits can be extended to word or longword, or lower 16 bits
to longword.
(EAd) (sign extension) → (EAd)
Extends the lower 8 or 16 bits of data in a general register or a memory
location to word size by padding with signs.
The lower eight bits can be extended to word or longword, or lower 16 bits
to longword.
@ERd − 0, 1 → (<bit 7> of @EAd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
(EAd) × (EAs) + MAC → MAC
Performs signed multiplication on memory contents and adds the result to
the MAC.
0 → MAC
Clears the MAC to zero.