Table of Contents
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5.8.6
Interrupts Source Flag of Peripheral Modules .................................................. 119
Section 6 Bus Controller (BSC) ........................................................................ 121
6.1
Features............................................................................................................................. 121
6.2
Register Descriptions........................................................................................................ 124
6.2.1
Bus Width Control Register (ABWCR)............................................................ 124
6.2.2
Access State Control Register (ASTCR) .......................................................... 126
6.2.3
Wait Control Registers A and B (WTCRA, WTCRB) ..................................... 127
6.2.4
Read Strobe Timing Control Register (RDNCR) ............................................. 132
CS Assertion Period Control Registers (CSACR) ............................................ 133
6.2.5
6.2.6
Idle Control Register (IDLCR) ......................................................................... 135
6.2.7
Bus Control Register 1 (BCR1) ........................................................................ 137
6.2.8
Bus Control Register 2 (BCR2) ........................................................................ 139
6.2.9
Endian Control Register (ENDIANCR) ........................................................... 140
6.2.10
SRAM Mode Control Register (SRAMCR) ..................................................... 141
6.2.11
Burst ROM Interface Control Register (BROMCR) ........................................ 142
6.2.12
Address/Data Multiplexed I/O Control Register (MPXCR) ............................. 144
6.3
Bus Configuration............................................................................................................. 145
6.4
Multi-Clock Function and Number of Access Cycles ...................................................... 146
6.5
External Bus ..................................................................................................................... 150
6.5.1
Input/Output Pins.............................................................................................. 150
6.5.2
Area Division.................................................................................................... 153
6.5.3
Chip Select Signals ........................................................................................... 154
6.5.4
External Bus Interface ...................................................................................... 155
6.5.5
Area and External Bus Interface ....................................................................... 159
6.5.6
Endian and Data Alignment.............................................................................. 163
6.6
Basic Bus Interface ........................................................................................................... 167
6.6.1
Data Bus ........................................................................................................... 167
6.6.2
I/O Pins Used for Basic Bus Interface .............................................................. 167
6.6.3
Basic Timing..................................................................................................... 168
6.6.4
Wait Control ..................................................................................................... 174
6.6.5
Read Strobe (RD) Timing................................................................................. 176
6.6.6
Extension of Chip Select (CS) Assertion Period............................................... 177
6.7
Byte Control SRAM Interface .......................................................................................... 179
6.7.1
Byte Control SRAM Space Setting................................................................... 179
6.7.2
Data Bus ........................................................................................................... 179
6.7.3
I/O Pins Used for Byte Control SRAM Interface ............................................. 180
6.7.4
Basic Timing..................................................................................................... 181
6.7.5
Wait Control ..................................................................................................... 183
6.7.6
Read Strobe (RD) ............................................................................................. 185
Rev.2.00 Jun. 28, 2007 Page xii of xxii
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