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Section 5 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program execution state
No
Interrupt generated?
Yes
Yes
NMI
No
No
I = 0
Pending
Yes
No
IRQ0
No
Yes
IRQ1
Yes
SSTXI2
Yes
Save PC and CCR
I ← 1
Read vector address
Branch to interrupt handling routine
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0
Rev.2.00 Jun. 28, 2007 Page 107 of 666
REJ09B0311-0200
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