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A block diagram of the bus controller is shown in figure 6.1.
Internal bus
control signals
CPU bus mastership acknowledge signal
DTC bus mastership acknowledge signal
CPU bus mastership request signal
DTC bus mastership request signal
Internal data bus
[Legend]
ABWCR:
Bus width control register
ASTCR:
Access state control register
WTCRA:
Wait control register A
WTCRB:
Wait control register B
RDNCR:
Read strobe timing control register
CS assertion period control register
CSACR:
CPU address bus
DTC address bus
Internal bus
control unit
Internal
bus
arbiter
Control register
Figure 6.1 Block Diagram of Bus Controller
Address
selecter
ABWCR
ASTCR
WTCRA
WTCRB
RDNCR
CSACR
IDLCR:
Idle control register
BCR1:
Bus control register 1
BCR2:
Bus control register 2
ENDIANCR:
Endian control register
SRAMCR:
SRAM mode control register
BROMCR:
Burst ROM interface control register
MPXCR:
Address/data multiplexed I/O control register
Rev.2.00 Jun. 28, 2007 Page 123 of 666
Section 6 Bus Controller (BSC)
Area decoder
External bus
control unit
External bus
arbiter
IDLCR
BCR1
BCR2 ENDIANCR
SRAMCR
BROMCR
MPXCR
REJ09B0311-0200
CS7 to CS0
External bus
control signals
WAIT
BREQ
BACK
BREQO
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