Bus Control Register 2 (Bcr2) - Renesas H8SX/1650 Hardware Manual

6.2.8

Bus Control Register 2 (BCR2)

BCR2 is used for bus arbitration control of the CPU and DTC, and enabling/disabling of the write
data buffer function to the peripheral modules.
Bit 7

Bit Name
Initial Value 0
R/W R
Bit Bit Name

7, 6

5
4 IBCCS

3, 2

1
0 PWDBE
6 5
 
0 0
R R/W
Initial
Value R/W Description
All 0 R Reserved
These are read-only bits and cannot be modified.
0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
0 R/W Internal Bus Cycle Control Select
Selects the internal bus arbiter function.
0: Releases the bus mastership according to the priority
1: Executes the bus cycles alternatively when a CPU bus
All 0 R Reserved
These are read-only bits and cannot be modified.
1 R/W Reserved
This bit is always read as 1. The write value should
always be 1.
0 R/W Peripheral Module Write Data Buffer Enable
Specifies whether or not to use the write data buffer
function for the peripheral module write cycles.
0: Write data buffer function not used
1: Write data buffer function used
4 3

IBCCS
0 0
R/W R
mastership request conflicts with a DTC bus
mastership request
Rev.2.00 Jun. 28, 2007 Page 139 of 666
Section 6 Bus Controller (BSC)
2 1
 
PWDBE
0 1
R R/W R/W
REJ09B0311-0200
0
0