Address/Data Multiplex; Data Bus - Renesas H8SX/1650 Hardware Manual

Section 6 Bus Controller (BSC)
6.9.2

Address/Data Multiplex

In the address/data multiplexed I/O space, data bus is multiplexed with address bus. Table 6.18
shows the relationship between the bus width and address output.
Table 6.18 Address/Data Multiplex
Bus Width Cycle
PI7
8 bits
Address
Data
16 bits Address A15
Data
D15
6.9.3

Data Bus

The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access
space or 16-bit access space by the ABWHn and ABWLn bits (n = 3 to 7) in ABWCR.
For the 8-bit access space, D7 to D0 are valid for both address and data. For 16-bit access space,
D15 to D0 are valid for both address and data. If the address/data multiplexed I/O space is
accessed, the corresponding address will be output to the address bus.
For details on access size and data alignment, see section 6.5.6, Endian and Data Alignment.
Rev.2.00 Jun. 28, 2007 Page 190 of 666
REJ09B0311-0200
PI6 PI5 PI4 PI3
    
    
A14 A13 A12 A11
D14 D13 D12 D11
Data Pins
PI2 PI1 PI0 PH7 PH6
  
A7 A6
  
D7 D6
A10 A9 A8 A7 A6
D10 D9 D8 D7 D6
PH5 PH4 PH3 PH2 PH1
A5 A4 A3 A2 A1
D5 D4 D3 D1
D2
A5 A4 A3 A1
A2
D5 D4 D3 D2 D1
PH0
A0
D0
A0
D0