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Section 17 Clock Pulse Generator
Table 17.2 Crystal Resonator Characteristics
Frequency (MHz)
R
Max. (Ω)
S
C
Max. (pF)
0
17.2.2
External Clock Input
An external clock signal can be input as shown in the examples in figure 17.4. If the XTAL pin is
left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is
input to the XTAL pin, make sure that the external clock is held high in standby mode.
For the input conditions of the external clock, refer to table 20.4, Clock Timing, in section 20.3.1,
Clock Timing. The input external clock should be from 8 to 18 MHz.
17.3
PLL Circuit
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 4. The frequency multiplication factor is fixed. The phase difference is controlled so that
the timing of the rising edge of the internal clock is the same as that of the EXTAL pin signal.
17.4
Frequency Divider
The frequency divider divides the PLL clock to generate a 1/2, 1/4, or 1/8 clock. After bits ICK2
to ICK0, PCK 2 to PCK0, and BCK2 to BCK0 are modified, this LSI operates at the modified
frequency.
Rev.2.00 Jun. 28, 2007 Page 558 of 666
REJ09B0311-0200
8
80
EXTAL
XTAL
(a) XTAL pin left open
EXTAL
XTAL
(b) Counter clock input on XTAL pin
Figure 17.4 External Clock Input (Examples)
12
60
7
External clock input
Open
External clock input
18
40
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