Renesas H8SX/1650 Hardware Manual page 13

6.7.7 Extension of Chip Select (CS) Assertion Period............................................... 185
6.8 Burst ROM Interface ........................................................................................................ 185
6.8.1 Burst ROM Space Setting................................................................................. 185
6.8.2 Data Bus............................................................................................................ 186
6.8.3 I/O Pins Used for Burst ROM Interface............................................................ 186
6.8.4 Basic Timing..................................................................................................... 187
6.8.5 Wait Control ..................................................................................................... 189
6.8.6 Read Strobe (RD) Timing................................................................................. 189
6.8.7 Extension of Chip Select (CS) Assertion Period............................................... 189
6.9 Address/Data Multiplexed I/O Interface........................................................................... 189
6.9.1 Address/Data Multiplexed I/O Space Setting ................................................... 189
6.9.2 Address/Data Multiplex .................................................................................... 190
6.9.3 Data Bus............................................................................................................ 190
6.9.4 I/O Pins Used for Address/Data Multiplexed I/O Interface .............................. 191
6.9.5 Basic Timing..................................................................................................... 192
6.9.6 Address Cycle Control...................................................................................... 194
6.9.7 Wait Control ..................................................................................................... 195
6.9.8 Read Strobe (RD) Timing................................................................................. 195
6.9.9 Extension of Chip Select (CS) Assertion Period............................................... 196
6.10 Idle Cycle.......................................................................................................................... 198
6.10.1 Operation .......................................................................................................... 198
6.10.2 Pin States in Idle Cycle ..................................................................................... 206
6.11 Bus Release....................................................................................................................... 207
6.11.1 Operation .......................................................................................................... 207
6.11.2 Pin States in External Bus Released State......................................................... 208
6.11.3 Transition Timing ............................................................................................. 209
6.12 Internal Bus....................................................................................................................... 210
6.12.1 Access to Internal Address Space ..................................................................... 210
6.13 Write Data Buffer Function .............................................................................................. 211
6.13.1 Write Data Buffer Function for External Data Bus........................................... 211
6.13.2 Write Data Buffer Function for Peripheral Modules ........................................ 212
6.14 Bus Arbitration ................................................................................................................. 213
6.14.1 Operation .......................................................................................................... 213
6.14.2 Bus Transfer Timing ......................................................................................... 214
6.15 Bus Controller Operation in Reset .................................................................................... 215
6.16 Usage Notes ...................................................................................................................... 215
Section 7 Data Transfer Controller (DTC) ........................................................217
7.1 Features............................................................................................................................. 217
7.2 Register Descriptions........................................................................................................ 219
Rev.2.00 Jun. 28, 2007 Page xiii of xxii