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Bit
Bit Name
7
IDLSEL7
6
IDLSEL6
5
IDLSEL5
4
IDLSEL4
3
IDLSEL3
2
IDLSEL2
1
IDLSEL1
0
IDLSEL0
6.2.7
Bus Control Register 1 (BCR1)
BCR1 is used for selection of the external bus released state protocol, enabling/disabling of the
write data buffer function, and enabling/disabling of the WAIT pin input.
Bit
15
Bit Name
BRLE
Initial Value
0
R/W
R/W
Bit
7
Bit Name
Initial Value
0
R/W
R/W
Bit
Bit Name
15
BRLE
Initial
Value
R/W
Description
0
R/W
Idle Cycle Number Select
0
R/W
Specifies the number of idle cycles to be inserted for
each area for the idle insertion condition specified by
0
R/W
IDLS1 and IDLS0.
0
R/W
0: Number of idle cycles to be inserted for area n is
0
R/W
0
R/W
1: Number of idle cycles to be inserted for area n is
0
R/W
0
R/W
(n = 7 to 0)
14
13
BREQOE
0
0
R/W
R
6
5
0
0
R/W
R
Initial
Value
R/W
Description
0
R/W
External Bus Release Enable
Enables/disables external bus release.
0: External bus release disabled
1: External bus release enabled*
To set this bit to 1, the ICR bit of the corresponding pin
should be specified to 1. For details, see section 8, I/O
ports.
specified by IDLCA1 and IDLCA0.
specified by IDLCB1 and IDLCB0.
12
11
0
0
R
R/W
4
3
0
0
R
R
BREQ, BACK, and BREQO pins can be used as I/O
ports
Rev.2.00 Jun. 28, 2007 Page 137 of 666
Section 6 Bus Controller (BSC)
10
9
WDBE
WAITE
0
0
R/W
R/W
2
1
0
0
R
R
REJ09B0311-0200
8
0
R/W
0
0
R
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