Renesas H8SX/1650 Hardware Manual page 440

Section 11 8-Bit Timers (TMR)
Bit Bit Name
6 CMIEA
5 OVIE
4 CCLR1
3 CCLR0
2 CKS2
1 CKS1
0 CKS0
Note: To use an external reset or external clock, the DDR and ICR bits in the corresponding
*
pin should be set to 0 and 1, respectively. For details, see section 8, I/O Ports.
Rev.2.00 Jun. 28, 2007 Page 418 of 666
REJ09B0311-0200
Initial
Value R/W Description
0 R/W Compare Match Interrupt Enable A
Selects whether CMFA interrupt requests (CMIA) are
enabled or disabled when the CMFA flag in TCSR is set
to 1.
0: CMFA interrupt requests (CMIA) are disabled
1: CMFA interrupt requests (CMIA) are enabled
0 R/W Timer Overflow Interrupt Enable
Selects whether OVF interrupt requests (OVI) are
enabled or disabled when the OVF flag in TCSR is set
to 1.
0: OVF interrupt requests (OVI) are disabled
1: OVF interrupt requests (OVI) are enabled
0 R/W Counter Clear 1 and 0*
0 R/W These bits select the method by which TCNT is cleared.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared at rising edge (TMRIS in TCCR is cleared
0 R/W Clock Select 2 to 0*
0 R/W These bits select the clock input to TCNT and count
condition. See table 11.2.
0 R/W
to 0) of the external reset input or when the external
reset input is high (TMRIS in TCCR is set to 1)