Table of Contents
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Section 1 Overview
Module/
Classification
Function
External bus
Bus
extension
controller
(BSC)
Clock
Clock pulse
generator
(CPG)
A/D converter
A/D
converter
(ADC)
Rev.2.00 Jun. 28, 2007 Page 4 of 666
REJ09B0311-0200
Description
Bus formats
•
External memory interfaces (for the connection of ROM, burst
ROM, SRAM, and byte control SRAM)
•
Address/data bus format: Support for both separate and
multiplexed buses (8-bit access or 16-bit access)
•
Endian conversion function for connecting devices in little-
endian format
•
One clock generation circuit available
•
Separate clock signals are provided for each of functional
modules (detailed below) and each is independently specifiable
(multi-clock function)
System-intended data transfer modules, i.e. the CPU, runs
in synchronization with the system clock (Iφ): 8 to 50 MHz
Internal peripheral functions run in synchronization with the
peripheral module clock (Pφ): 8 to 35 MHz
Modules in the external space are supplied with the external
bus clock (Bφ): 8 to 50 MHz
•
Includes a PLL frequency multiplication circuit and frequency
divider, so the operating frequency is selectable
•
Five low-power-consumption modes: Sleep mode, module-stop
mode, all-module-clock-stop mode, software standby mode,
and hardware standby mode
•
10-bit resolution × eight input channels
•
Sample and hold function included
•
Conversion time: 7.4 µs per channel (with peripheral module
clock (Pφ) at 35-MHz operation)
•
Two operating modes: single mode and scan mode
•
Three ways to start A/D conversion: software, timer (TPU/TMR)
trigger, and external trigger
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