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Classification
Pin Name
BACK
Bus control
BS-A/BS-B
AS
AH
RD
RD/WR
LHWR
LLWR
LUB
LLB
CS0
CS1
CS2-A/CS2-B
CS3
CS4-A/CS4-C
CS5-A/CS5-B/
CS5-C/CS5-D
CS6-A/CS6-B/
CS6-C/CS6-D
CS7-A/CS7-B/
CS7-C
WAIT
I/O
Description
Output
Bus acknowledge signal, which indicates that the bus has
been released.
Output
Indicates the start of a bus cycle.
Output
Strobe signal which indicates that the output address on the
address bus is valid in access to the basic bus interface or
byte control SRAM interface space.
Output
This signal is used to hold the address when accessing the
address-data multiplexed I/O interface space.
Output
Strobe signal which indicates that reading from the basic
bus interface space is in progress.
Output
Indicates the direction (input or output) of the data bus.
Output
Strobe signal which indicates that the higher-order byte
(D15 to D8) is valid in access to the basic bus interface
space.
Output
Strobe signal which indicates that the lower-order byte (D7
to D0) is valid in access to the basic bus interface space.
Output
Strobe signal which indicates that the higher-order byte
(D15 to D8) is valid in access to the byte control SRAM
interface space.
Output
Strobe signal which indicates that the lower-order byte (D7
to D0) is valid in access to the byte control SRAM interface
space.
Output
Select signals for areas 0 to 7.
Input
Requests wait cycles in access to the external space.
Section 1 Overview
Rev.2.00 Jun. 28, 2007 Page 11 of 666
REJ09B0311-0200
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