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Section 6 Bus Controller (BSC)
Table 6.3
Pin Functions in Each Interface
Initial State
Pin Name
16
8
Output Output
Bφ
CS0
Output Output
CS1
CS2
CS3
CS4
CS5
CS6
CS7
BS
RD/WR
AS
Output Output
AH
RD
Output Output
LHWR/LUB Output Output
LLWR/LLB
Output Output
WAIT
[Legend]
O:
Used as a bus control signal
:
Not used as a bus control signal (used as a port input when initialized)
Rev.2.00 Jun. 28, 2007 Page 152 of 666
REJ09B0311-0200
Control
Basic Bus
Single-
16
8
16
Chip
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Byte
Address/Data
Burst
Multiplexed
SRAM
ROM
16
8
16
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
8
Remarks
O
O
O
O
O
O
O
O
O
O
O
O
Controlled by
WAITE
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