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2.5.1
General Registers
The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike
and can be used as both address registers and data registers. When a general register is used as a
data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.10 illustrates the
usage of the general registers.
When the general registers are used as 32-bit registers or address registers, they are designated by
the letters ER (ER0 to ER7).
The ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7)
and R (R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-
bit registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H)
and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of
sixteen 8-bit registers.
The general registers ER (ER0 to ER7), R (R0 to R7), and RL (R0L to R7L) are also used as index
registers. The size in the operand field determines which register is selected.
The usage of each register can be selected independently.
•
Address registers
•
32-bit registers
•
32-bit index registers
General registers ER
(ER0 to ER7)
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.11 shows the
stack.
•
16-bit registers
General registers E
(E0 to E7)
•
16-bit registers
•
16-bit index registers
General registers R
(R0 to R7)
Figure 2.10 Usage of General Registers
•
8-bit registers
General registers RH
(R0H to R7H)
•
8-bit registers
•
8-bit index registers
General registers RL
(R0L to R7L)
Rev.2.00 Jun. 28, 2007 Page 25 of 666
REJ09B0311-0200
Section 2 CPU
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