Renesas H8SX/1650 Hardware Manual page 618

Section 19 List of Registers
Register Name
Timer control register_2
Timer mode register_2
Timer I/O control register_2
Timer interrupt enable register_2
Timer status register_2
Timer counter_2
Timer general register A_2
Timer general register B_2
Timer control register_3
Timer mode register_3
Timer I/O control register H_3
Timer I/O control register L_3
Timer interrupt enable register_3
Timer status register_3
Timer counter_3
Timer general register A_3
Timer general register B_3
Timer general register C_3
Timer general register D_3
Note: * When the same output trigger is specified for pulse output groups 2 and 3 by the PCR
setting, the NDRH address is H'FFF7C. When different output triggers are specified, the
NDRH addresses for pulse output groups 2 and 3 are H'FFF7E and H'FFF7C,
respectively. Similarly, when the same output trigger is specified for pulse output groups
0 and 1 by the PCR setting, the NDRL address is H'FFF7D. When different output
triggers are specified, the NDRL addresses for pulse output groups 0 and 1 are H'FFF7F
and H'FFF7D, respectively.
Rev.2.00 Jun. 28, 2007 Page 596 of 666
REJ09B0311-0200
Number
Abbreviation of Bits
TCR_2 8
TMDR_2 8
TIOR_2 8
TIER_2 8
TSR_2 8
TCNT_2 16
TGRA_2 16
TGRB_2 16
TCR_3 8
TMDR_3 8
TIORH_3 8
TIORL_3 8
TIER_3 8
TSR_3 8
TCNT_3 16
TGRA_3 16
TGRB_3 16
TGRC_3 16
TGRD_3 16
Address Module
H'FFFE0 TPU_2
H'FFFE1 TPU_2
H'FFFE2 TPU_2
H'FFFE4 TPU_2
H'FFFE5 TPU_2
H'FFFE6 TPU_2
H'FFFE8 TPU_2
H'FFFEA TPU_2
H'FFFF0 TPU_3
H'FFFF1 TPU_3
H'FFFF2 TPU_3
H'FFFF3 TPU_3
H'FFFF4 TPU_3
H'FFFF5 TPU_3
H'FFFF6 TPU_3
H'FFFF8 TPU_3
H'FFFFA TPU_3
H'FFFFC TPU_3
H'FFFFE TPU_3
Access
Data Cycles
Width (Read/Write)
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ
16 2Pφ/2Pφ