Renesas H8SX/1650 Hardware Manual page 59

Renesas 32-bit cisc microcomputer h8sx family / h8sx/1600 series
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Table 2.2
Combinations of Instructions and Addressing Modes (2)
Classifi-
cation
Instruction
Branch
BRA/BS,
BRA/BC
BSR/BS,
BSR/BC
Bcc
BRA
BRA/S
JMP
BSR
JSR
RTS, RTS/L
System
TRAPA
control
RTE, RTE/L
[Legend]
d:
d:8 or d:16
Note:
@(d:8, PC) is only available.
*
Size
@ERn
@(d,PC)
O
O
O
O
O*
O
O
O
Addressing Mode
@(RnL.B/
Rn.W/
ERn.L,
PC)
@aa:24
@aa:32
O
O
O
O
O
Rev.2.00 Jun. 28, 2007 Page 37 of 666
Section 2 CPU
@@aa:8
@@vec:7
O
O
O
O
O
O
O
REJ09B0311-0200

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