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Section 2 CPU
• Exception Handling Vector Table and Memory Indirect Branch Addresses
In normal mode, the top area starting at H'0000 is allocated to the exception handling vector
table. One branch address is stored per 16 bits. The structure of the exception handling vector
table is shown in figure 2.2.
Figure 2.2 Exception Handling Vector Table (Normal Mode)
The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are
used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code
specifies a memory location. Execution branches to the address contained in the memory location.
• Stack Structure
The stack structure of PC at a subroutine branch and that of PC and CCR at an exception
handling branch are shown in figure 2.3. The PC contents are saved or restored in 16-bit units.
SP
Notes: 1.
Rev.2.00 Jun. 28, 2007 Page 18 of 666
REJ09B0311-0200
H'0000
Reset exception vector
H'0001
H'0002
Reset exception vector
H'0003
PC
(16 bits)
(a) Subroutine Branch
When EXR is not used it is not stored on the stack.
2.
SP when EXR is not used.
3.
Ignored on return.
Figure 2.3 Stack Structure in Normal Mode
Exception
vector table
SP
EXR*
Reserved*
2
*
(SP
)
CCR
CCR*
PC
(16 bits)
(b) Exception Handling
1
1
3
,*
3
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