Receive Data Sampling Timing And Reception Margin - Renesas H8SX/1650 Hardware Manual

13.7.4

Receive Data Sampling Timing and Reception Margin

Only the internal clock generated by the on-chip baud rate generator can be used as a transfer
clock in smart card interface mode. In this mode, the SCI can operate on a basic clock with a
frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 bit settings
(the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the
falling edge of the start bit is sampled using the basic clock in order to perform internal
synchronization. Receive data is sampled on the 16th, 32nd, 186th and 128th rising edges of the
basic clock so that it can be latched at the middle of each bit as shown in figure 13.25. The
reception margin here is determined by the following formula.
M = | (0.5 –
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Duty cycle of clock (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is
determined by the formula below.
M = ( 0.5 –
2 × 372
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode
1
) – (L – 0.5) F –
2N
1
) × 100% = 49.866%
372 clock cycles
186 clock
cycles
0 185
371
Start bit
(When Clock Frequency is 372 Times the Bit Rate)
Section 13 Serial Communication Interface (SCI)
| D – 0.5 |
(1 + F ) | × 100%
N
185
0
D0
Rev.2.00 Jun. 28, 2007 Page 509 of 666
371 0
D1
REJ09B0311-0200