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Section 6 Bus Controller (BSC)
Bφ
WAIT
Address
CSn
AS
UUB, ULB
RD/WR
RD
Read
Data bus
RD/WR
RD
Write
Data bus
BS
Notes: 1. Upward arrows indicate the timing of WAIT pin sampling.
2. n = 0 to 7
Figure 6.25 Example of Wait Cycle Insertion Timing
Rev.2.00 Jun. 28, 2007 Page 184 of 666
REJ09B0311-0200
Wait by
program wait
T
T
T
1
2
pw
High level
Write data
Wait by WAIT pin
T
T
T
tw
tw
3
Read data
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