Timer Mode Register (Tmdr) - Renesas H8SX/1650 Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.2

Timer Mode Register (TMDR)

TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each
channel. TMDR register settings should be made only while TCNT operation is stopped.
Bit 7
Bit Name
Initial Value 1
R/W R
Bit Bit Name

7, 6
5 BFB
4 BFA
3 MD3
2 MD2
1 MD1
0 MD0
Rev.2.00 Jun. 28, 2007 Page 318 of 666
REJ09B0311-0200
6 5
BFB
1 0
R R/W
Initial
Value R/W Description
All 1 R Reserved
These are read-only bits and cannot be modified.
0 R/W Buffer Operation B
Specifies whether TGRB is to normally operate, or TGRB
and TGRD are to be used together for buffer operation.
When TGRD is used as a buffer register, TGRD input
capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is
reserved. It is always read as 0 and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
0 R/W Buffer Operation A
Specifies whether TGRA is to normally operate, or TGRA
and TGRC are to be used together for buffer operation.
When TGRC is used as a buffer register, TGRC input
capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is
reserved. It is always read as 0 and cannot be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
0 R/W Modes 3 to 0
0 R/W Set the timer operating mode.
0 R/W MD3 is a reserved bit. The write value should always be
0. See table 9.12 for details.
0 R/W
4 3
BFA MD3
0 0
R/W R/W
2 1
MD2 MD1
0 0
R/W R/W
0
MD0
0
R/W