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Section 7 Data Transfer Controller (DTC)
Figure 7.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to
the data area*. When the transfer information is allocated to the on-chip RAM, a 32-bit bus
connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC
transfer information.
Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in SYSCR
must be set to 1.
Interrupt controller
DTCCR
DTC activation request
vector number
CPU interrupt request
Interrupt source clear
request
External
memory
External device
(memory mapped)
[Legend]
MRA, MRB:
DTC mode registers A, B
SAR:
DTC source address register
DAR:
DTC destination address register
CRA, CRB:
DTC transfer count registers A, B
DTCERA to DTCERH:
DTC enable registers A to H
DTCCR:
DTC control register
DTCVBR:
DTC vector base register
Rev.2.00 Jun. 28, 2007 Page 218 of 666
REJ09B0311-0200
On-chip
RAM
On-chip
peripheral
module
8
Bus controller
DTCVBR
Figure 7.1 Block Diagram of DTC
DTC
Register
control
Activation
control
Interrupt
control
Bus interface
REQ
ACK
MRA
MRB
SAR
DAR
CRA
CRB
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