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Section 2 CPU
2.8.5
Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment,
or Post-Decrement—@ERn+, @−ERn, @+ERn, or @ERn−
(1)
Register indirect with post-increment—@ERn+
The operand value is the contents of a memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field in the instruction code. After the
memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is
stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for
longword access.
(2)
Register indirect with pre-decrement—@−ERn
The operand value is the contents of a memory location which is pointed to by the following
operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ERn)
which is specified by the register field in the instruction code. After that, the subtraction result is
stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for
longword access.
(3)
Register indirect with pre-increment—@+ERn
The operand value is the contents of a memory location which is pointed to by the following
operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn) which is
specified by the register field in the instruction code. After that, the sum is stored in the address
register. The value added is 1 for byte access, 2 for word access, or 4 for longword access.
(4)
Register indirect with post-decrement—@ERn−
The operand value is the contents of a memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field in the instruction code. After the
memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the
subtraction result is stored in the address register. The value subtracted is 1 for byte access, 2 for
word access, or 4 for longword access.
If the contents of a general register which is also used as an address register is written to memory
using this addressing mode, data to be written is the contents of the general register after
calculating an effective address. If the same general register is specified in an instruction and two
effective addresses are calculated, the contents of the general register after the first calculation of
an effective address is used in the second calculation of an effective address.
Rev.2.00 Jun. 28, 2007 Page 52 of 666
REJ09B0311-0200
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