Renesas H8SX/1650 Hardware Manual page 534

Section 13 Serial Communication Interface (SCI)
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
TDRE
Transfer from TDR to TSR
TEND
FER/ERS
Figure 13.26 Data Re-Transfer Operation in SCI Transmission Mode
Note that the TEND flag is set in different timings depending on the GM bit setting in SMR.
Figure 13.27 shows the TEND flag set timing.
I/O data
TXI
(TEND interrupt)
GM = 0
GM = 1
[Legend]
Ds:
D0 to D7: Data bits
Dp:
DE:
Figure 13.27 TEND Flag Set Timing during Transmission
Rev.2.00 Jun. 28, 2007 Page 512 of 666
REJ09B0311-0200
[1]
Ds D0 D1 D2
Start bit
Parity bit
Error signal
Retransfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transfer from TDR to TSR
[2]
D3 D4 D5 D6 D7
12.5 etu
11.0 etu
(n + 1) th
transfer frame
(DE)
Ds D0 D1 D2 D3 D4
Transfer from TDR to TSR
[4]
[3]
Dp DE
Guard time