Bφ Clock Output Control - Renesas H8SX/1650 Hardware Manual

18.10 Bφ Clock Output Control
Output of the Bφ clock can be controlled by bits PSTOP1 and POSEL1 in SCKCR, and DDR for
the corresponding PA7 pin.
Clearing both bits PSTOP1 and POSEL1 to 0 enables the Bφ clock output on the PA7 pin. When
bit PSTOP1 is set to 1, the Bφ clock output stops at the end of the bus cycle, and the Bφ clock
output goes high. When DDR for the PA7 pin is cleared to 0, the Bφ clock output is disabled and
the pin becomes an input port.
Tables 18.3 shows the states of the Bφ pin in each processing state.
Table 18.3 Bφ Pin (PA7) State in Each Processing State
Register Setting Value
DDR PSTOP1
X
0
0
1
0
1
1
1
Normal
Operating
POSEL1 State
X
Hi-Z
0
Bφ output
1
Setting
prohibited
X
High
All-
Module-
Sleep Clock-
Mode Stop Mode OPE = 0
Hi-Z Hi-Z
Bφ output Bφ output
Setting Setting
prohibited prohibited
High High
Rev.2.00 Jun. 28, 2007 Page 585 of 666
Section 18 Power-Down States
Software
Standby Mode
OPE = 1
Hi-Z Hi-Z
High High
Setting Setting
prohibited prohibited
High High
REJ09B0311-0200
Hardware
Standby
Mode
Hi-Z
Hi-Z
Setting
prohibited
Hi-Z