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(2)
Write after Read
If an external write occurs after an external read while bit IDLS0 in IDLCRis set to 1, idle cycles
specified by bits IDLCA1 and IDLCA0 when bit IDSELn in IDLCR is cleared to 0 when
IDLSELn = 0,or bits IDLCB1 and IDLCB0 when IDLSELn is set to 1 are inserted at the start of
the write cycle (n = 0 to 7).
Figure 6.35 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a conflict occurs in bus cycle B between the read data from ROM
and the CPU write data. In (b), an idle cycle is inserted, and a data conflict is prevented.
Bφ
Address bus
CS (area A)
CS (area B)
RD
LLWR
Data bus
(a) No idle cycle inserted
Figure 6.35 Example of Idle Cycle Operation (Write after Read)
Bus cycle B
Bus cycle A
T
T
T
T
T
1
2
3
1
Data hold time is long.
(IDLS0 = 0)
Bus cycle A
T
2
1
Data conflict
(b) Idle cycle inserted
(IDLS0 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Rev.2.00 Jun. 28, 2007 Page 201 of 666
Section 6 Bus Controller (BSC)
Bus cycle B
T
T
T
T
2
3
i
1
REJ09B0311-0200
T
2
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