Receive Data Sampling Timing And Reception Margin In Asynchronous Mode - Renesas H8SX/1650 Hardware Manual

13.4.2

Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse of the
basic clock, data is latched at the middle of each bit, as shown in figure 13.3. Thus the reception
margin in asynchronous mode is determined by formula (1) below.
M = (0.5 – |
M: Reception margin
N: Ratio of bit rate to clock (N = 16)
D: Duty cycle of clock (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the
formula below.
M = ( 0.5 –
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode
1
) – (L – 0.5) F –
2N
1
) × 100[%] = 46.875%
2 × 16
16 clocks
8 clocks
0 7
Start bit
Section 13 Serial Communication Interface (SCI)
| D – 0.5 |
(1 + F ) | × 100
N
15 0
D0
Rev.2.00 Jun. 28, 2007 Page 483 of 666
... Formula (1)
[%]
7 15 0
D1
REJ09B0311-0200