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Section 5 Interrupt Controller
(3)
Operation Order
If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the
CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is
selected as the DTC activation source or CPU interrupt source, respective operations are
performed independently.
Table 5.6 lists the selection of interrupt sources and interrupt source clear control by means of the
setting of the DTCE bit in DTCERA to DTCERH of the DTC, and the DISEL bit in MRB of the
DTC.
Table 5.6
Interrupt Source Selection and Clear Control
DTC Setting
DTCE
0
1
[Legend]
√:
The corresponding interrupt is used. The interrupt source is cleared.
(The interrupt source flag must be cleared in the CPU interrupt handling routine.)
O:
The corresponding interrupt is used. The interrupt source is not cleared.
X:
The corresponding interrupt is not available.
Don't care.
*:
(4)
Usage Note
The interrupt sources of the SCI and A/D converter are cleared according to the setting shown in
table 5.6, when the DTC reads/writes the prescribed register.
To initiate multiple channels for the DTC with the same interrupt, the same priority should be
assigned.
Rev.2.00 Jun. 28, 2007 Page 114 of 666
REJ09B0311-0200
DISEL
*
0
1
Interrupt Source Selection/Clear Control
DTC
X
√
O
CPU
√
X
√
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