Register Descriptions - Renesas H8SX/1650 Hardware Manual

Reset state
Program execution state
Notes: 1. NMI, IRQ0 to IRQ11, 8-bit timer interrupts, and watchdog timer interrupts.
The 8-bit timer is valid when bits MSTPCRA11 to MSTPCRA8 are all cleared to 0.
2. NMI and IRQ0 to IRQ11. Note that IRQ is valid only when the corresponding bit in SSIER is set to 1.
From any state, a transition to hardware standby mode occurs when STBY is driven low.
From any state except for hardware standby mode, a transition to the reset state occurs when RES is driven low.
3. When the SLPIE bit is cleared to 0
18.2

Register Descriptions

The registers related to the power-down state are shown below. For details on the system clock
control register (SCKCR), see section 17.1.1, System Clock Control Register (SCKCR).
• Standby control register (SBYCR)
• Module stop control register A (MSTPCRA)
• Module stop control register B (MSTPCRB)
• Module stop control register C (MSTPCRC)
STBY pin = high
RES pin = low
RES pin = high
Transition after exception handling
Figure 18.1 Mode Transitions
STBY pin = low
Hardware standby mode
SSBY = 0
SLEEP
3
instruction*
SSBY = 0, ACSE = 1
All interrupts
MSTPCR = H'F[0-F]FFFFFF
3
SLEEP instruction*
1
Interrupt*
SLEEP
3
instruction*
SSBY = 1
External
2
interrupt*
Software standby mode
Rev.2.00 Jun. 28, 2007 Page 565 of 666
Section 18 Power-Down States
Sleep mode
All-module-clock-
stop mode
Program halted state
REJ09B0311-0200